1. Field of the Invention
The present invention relates to a method of fabricating a contact hole, and particularly to a method of fabricating a node contact hole.
2. Description of the Prior Art
Recently, ultra large scale integration (ULSI) semiconductor technologies have dramatically increased the integrated circuit density on the chips formed on the semiconductor substrate. This increase in circuit density has resulted from downsizing of the individual devices and the resulting increase in device packing density. The reduction in device size was achieved predominantly by recent advances in high resolution photolithography, directional (anisotropic) plasma etching, and other semiconductor technology innovations. However, future requirements for even greater circuit density is putting additional demand on the semiconductor processing technologies and on device electrical requirements.
The rapidly increasing integrated circuit in the number of cells on the DRAM chip and the corresponding reduction in physical size of the capacitor, it is becoming increasingly difficult to fabricate a node contact hole in the capacitor. FIGS. 1A and 1B shows the cross-sectional view of a traditional node contact hole. At first, the polysilicon layer 110 is formed on the interpoly dielectric layer 100. Afterwards, the trench 120 is formed in polysilicon layer 110, as shown in FIG. 1A. Next, a portion of the interpoly dielectric layer 100 is etched to expose the land pad 130, using the polysilicon layer 110 as a hard mask. Then, the polysilicon layer 110 is removed on the interpoly dielectric layer 100. Finally, the node contact hole 140 is formed in the interpoly dielectric layer 100, as shown in FIG. 1B. Due to this contact hole 140 will not obtain the linewidth of 0.1 .mu.m. Thus, this present invention is disclosed by applying novel processes, and improving the disadvantage.